A Novel Sequence Generator Replacing LFSR For Hardwired BIST Of SRAM

This paper has emphasis on the novel sequence generation for the hardwired built in self test (BIST) of static random access memory (SRAM). It reduces the testing time of SRAM by generating all the pattern sequence in less time. BIST is a design technique that allows a circuit to test itself. Linear feedback shift register (LFSR) was used for the sequence generation in the BIST but novel sequence generator is better than LFSR for BIST of SRAM. The novel designing of the sequence generator has done with the help of synchronous up and down counter. The up and down counter has used here is of 4 bits and the corresponding addresses are also of 4 bits but there is a unique transition take place. The switching between the sequence of the up and down counter generates the sequence which is fulfilling the requirement for the BIST purpose. This requires very little hardware overhead so the area is reduced which on the other hand reduced cost as well as power. The necessary sequences which have required for detecting the faults such stuck at/open faults, transition faults, etc. It can be detected easily with the help of this sequence generator. The large number of sequences can be generated with the help of cascading the smaller module. It is more efficient than LFSR. The whole designing has done in the 180 nm technology in Cadence’s spectre, virtuoso & assura tool.